The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a high-performance heterojunction field-effect transistor (HFET) with uniform electrical characteristics and a method of manufacturing the same.
Recent years have seen significant advances in the field of telecommunication. Among them are developments in portable terminal equipment represented by a mobile telephone, which has rapidly prevailed in the last few years. Since size reduction and performance enhancement are essential to a mobile telephone, a device smaller in size and higher in performance has been in increasing demand. In order to provide a mobile telephone smaller in size and higher in performance, a reduced voltage, as well as a single power source, is necessary. In the field of a mobile telephone, a power device using a positive single power source is under vigorous development so as to replace a conventional power device using positive and negative double power sources. For the purpose of implementing an operation using a positive single power source, however, a device of even higher performance is required. Although a MESFET produced by ion implantation has conventionally been prevalent as a power FET, a JFET or an HFET has recently become an alternative to the MESFET, which has substantially reached a limit of performance enhancement.
With reference to the drawings, a conventional method of manufacturing an HFET will be described. FIGS. 26 and 27 are cross-sectional views sequentially illustrating the process steps of the conventional method of manufacturing an HFET. First, as shown in FIG. 26(a), a plurality of epitaxial layers 102, which are different from each other in composition and include a heterojunction, are grown, for example, by an MOCVD method on a semi-insulating GaAs substrate 101 such that a high-concentration N-type layer is formed as the uppermost layer thereof. Then, as shown in FIG. 26(b), mesa etching is performed with respect to the epitaxial layers 102 to implement element isolation.
Next, as shown in FIG. 26(c), ohmic electrodes 103, to be source/drain electrodes, are formed in respectively specified regions on the uppermost layer of the epitaxial layers 102.
Next, as shown in FIG. 26(d), a resist pattern 104 having an opening 104a in a gate-electrode formation region is formed by photolithography. Then, as shown in FIG. 27(a), recess etching is performed with respect to the gate-electrode formation region including the uppermost layer of the epitaxial layers 102, thereby forming a recess-etched portion 102a.
Next, as shown in FIG. 27(b), a conductive film is deposited over the semi-insulating GaAs substrate 101 to be filled into the opening 104a of the resist pattern 104. A gate electrode 105 is formed after the resist pattern 104 has been lifted off, whereby the manufacturing of the HFET is completed.
However, the conventional method of manufacturing an HFET has the problem in that the electrical characteristics of the resulting HFET are seriously affected by the controllability and the uniformity of recess etching illustrated in FIG. 27(a). In a power HFET used in a mobile telephone, for example, the threshold voltage Vth, representing the characteristics of the FET, should be regulated at -0.2.+-.0.1 V. This indicates that the depth of the recess-etched portion 102 should be controlled with a tolerance of .+-.1 nm. However, it is extremely difficult to control the depth with a tolerance of .+-.1 nm across the surface of a wafer by recess etching based on wet-etching technology used commonly at present.